1. Field of the Invention
The present invention relates generally to the field of integrated circuits including a semiconductive substrate, such as a silicon wafer or chip, with vias formed therethrough and, more particularly, although not necessarily limited to, integrated circuits that include insulated vias filled with conductive material and methods for their fabrication.
2. State of the Art
In order to function, integrated circuits must be in electrical communication with signal inputs and outputs as well as power and ground connections external to the integrated circuit. For example, power and ground or other reference voltage must be supplied for operation of the integrated circuit, and other connections, such as for input, output and timing signals, may also be required. These connections are typically made through leads or other conductive elements connected to bond pads present on the surface of a die. Leads are typically connected to the bond pads by wire bonding, or welding a wire between a bond pad and an associated lead.
Conventionally, bond wires have an arc-like shape extending out from the active surface of the semiconductor die. The size, shape and length of these wires may impair the optimum operation of some integrated circuits due to resistance of the wire material, inductive effects of the wires and inconsistencies in wire lengths.
U.S. Pat. No. 6,198,168 to Geusic et al. represents one attempt to deal with the foregoing problem. The Geusic-type integrated circuits feature conductively filled vias that extend through a wafer or die. Each via is connected to bond pads at both surfaces of the die, allowing a metallization layer connected to a bond pad at one surface to be in electrical communication with a lead connected to the bond pad on the opposite surface. Such a design eliminates the need for wirebonds in close proximity to the integrated circuit. However, the transmission of an electrical current through the conductively filled vias creates an inductive effect within the die that may impair the function of the integrated circuit. The Geusic-type devices attempt to minimize this effect by oxidizing the wall surfaces of the via to provide an electrically insulating oxide coating prior to filling the via. While this approach reduces the inductive effect of a current through the die, it fails to completely eliminate it, especially where alternating current is applied.
Another approach to creating a lined via is to create a via through a substrate and then deposit a layer of dielectric material (or other desired material) over the surface of the substrate and into the via. The deposited layer is then removed down to the surface of the substrate, leaving only the material deposited in the via. This removal may be accomplished by an abrasive removal technique such as polishing, by chemical removal techniques such as etching, or by other suitable techniques. One example of the foregoing approach is disclosed in U.S. Pat. No. 6,157,081 to Nariman et al., the disclosure of which is hereby incorporated by reference herein in its entirety. The Nariman et al. deposition technique can be problematic as deposition of the dielectric material occurs on every exposed surface of the substrate. Further, the thickness of the dielectric material on the sidewalls of a via cannot be precisely controlled. Where the deposited dielectric material is relatively viscous and/or the diameter of the via is relatively small, the dielectric material may “pinch off” and form a plug at or near a mouth of the via at the surface of the substrate. This plug may extend only partway down the via. Such vias are then unusable, as either they are blocked by the dielectric material or they contain uncoated sidewall sections. Even where the technique is successful, the thickness of the coating can vary significantly along the sidewalls of the via, resulting in a similar variability in its dielectric or conductive properties.